This application claims the benefit of Korean Patent Application No. P2000-50907, filed on Aug. 30, 2000, which is hereby incorporated by reference.
1. Field of the Invention
This invention relates to driving circuitry for a liquid crystal display, and more particularly, to a shift register of a liquid crystal display driving circuit.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) displays pictures by varying light transmissivity in the liquid crystal with selective application of electric field to the liquid crystal panel. In a matrix type LCD, pixel cells are arranged at intersections between data lines and scanning lines (e.g., gate lines). The data lines receive picture data from a data driver while the scanning lines receive scanning pulses from a scanning driver. The scanning driver includes a plurality of shift registers that sequentially apply the scanning pulses to the scanning lines.
FIG. 1 is a block circuit diagram showing a configuration of a related art shift register. Referring to FIG. 1, the related art shift register includes n stages 21 to 2n in cascade configuration and connected to respective n row lines ROW1 to ROWn via output lines 41 to 4n. A start pulse SP is input to the first stage 21, and each of the second to n-th stages 22 to 2n receives an output signal from its respective previous stage. Each of stages 21 to 2n is coupled to a row line ROWi connected to a pixel train and is selected using two of four clock signals C1 to C4.
FIG. 2 is a detailed circuit diagram showing the i-th stage and (i+1)-th stage of the related art shift register. Referring to FIG. 2, the i-th stage 2i includes second and fourth NMOS transistors T2 and T4 connected to a ground voltage VSS, a third NMOS transistor T3 connected to a supply voltage VCC, fifth and sixth NMOS transistors T5 and T6 connected to the output line 4i, and a first NMOS transistor T1 supplied with an output signal gixe2x88x921 at the previous stage.
The output signal gixe2x88x921 present at the previous stage is applied to gate terminals of the first and fourth NMOS transistors T1 and T4. Drain terminals of the second NMOS transistor T2, the fourth NMOS transistor T4 and the sixth NMOS transistor T6 are connected to a ground voltage VSS. Gate terminals of the second and sixth NMOS transistors T2 and T6 are connected to a source terminal of the fourth NMOS transistor T4 and a drain terminal of the third NMOS transistor T3. The first and third clock signals C1 and C3 are applied to the i-th stage 2i, as shown in FIG. 2.
An operation process of the i-th stage 2i will be explained with reference to FIG. 3 below. First, the third clock signal C3 is applied to the gate terminal of the third NMOS transistor T3. If the third clock signal C3 is applied, then the third NMOS transistor T3 is turned on. When the third NMOS transistor T3 is turned on, a supply voltage VCC is applied to a second node P2 to turn on the second and sixth NMOS transistors T2 and T6. At this time, a first node P1 and the output line 4i are initialized at the ground voltage VSS.
Subsequently, the output signal gixe2x88x921 at the previous stage is applied as a start pulse. If the output signal gixe2x88x921 from the previous stage is applied, then the first and fourth NMOS transistors T1 and T4 are turned on. When the fourth NMOS transistors T4 is turned on, a second node P2 is connected to the ground voltage VSS to turn off the second and sixth NMOS transistors T2 and T6. On the other hand, when the first NMOS transistor T1 is turned on, the output signal gixe2x88x921 from the previous stage is applied to the first node P1. At this time, the fifth NMOS transistor T5 connected to the first node P1 is turned on.
After turning on the fifth NMOS transistor T5, the first clock signal C1 is applied to the source terminal of the fifth NMOS transistor T5. The first clock signal C1 applied upon turn-on of the fifth NMOS transistor T5 is applied to the output line 4i. In other words, the i-th output line 4i is selected. After the clock voltage signal C1 is applied to the output line 4i, the first clock signal C1 is inverted into a low logic and thus the output line 4i also is supplied with a logic low voltage (i.e., a ground voltage).
Typically, a gate line swing voltage of the related art LCD is approximately 20 to 25V. In order to fulfill this swing voltage, swing voltages of the clock signals C1 to C4 input to the shift register should be set to more than 20V.
When the shift register is configured with NMOS transistors as shown in FIG. 2, clock signals C1 to C4 of 0 to 20V should be inputted for an application of a swing voltage of 20V to the gate line. On the other hand, when the shift register is configured with PMOS transistors, clock signals C1 to C4 of xe2x88x928 to xe2x88x9212V should be inputted for an application of a swing voltage of 20V to the gate line. In other words, in the related art shift register, clock signals C1 to C4 having a large swing width are inputted from an external circuit (not shown) to the stages 21 to 2n.
The external circuit for supplying the clock signals C1 to C4 is configured within a single integrated circuit (IC) chip. The single IC chip generates clock signals C1 to C4 having a large swing width and applies them to the stages 21 to 2n.
However, while the external circuit of the related art (configured within the single IC chip) easily creates pulse signals having a low voltage (e.g., 0 to 10V), it has difficulty creating a voltage signal more than this low voltage or voltage signals at negative values. In other words, it is difficult to maintain reliable device characteristics according to the related art single IC chip because the external circuit has difficulty creating high voltages (e.g., more than 10V) and negative voltages. Thus, a high voltage or a negative voltage created by means of a single IC chip can cause erroneous operation resulting in adversely affected device characteristics.
Accordingly, the present invention is directed to a shift register circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
In one aspect of the present invention, a shift register provides a reduced swing width of a clock voltage.
Additional features and advantages of the invention will be set forth in the description that follows; and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages in accordance with the present invention, as embodied and broadly described, the shift register circuit according to the present invention includes a plurality of stages, each of the plurality of stages associated with a respective one of a plurality of scanning lines for generating a first driving signal in response to first and second clock signals, and a plurality of level shifters, each of the level shifters being connected between one of the plurality of stages and its associated scanning line for applying a second driving signal to the scanning line in response to the first driving signal, wherein the second driving signal has a larger swing width than the first driving signal.
In another aspect of the present invention, a shift register circuit of the present invention includes a plurality of stages, each of the plurality of stages associated with a respective one of a plurality of scanning lines for generating a first driving signal in response to first and second clock signals, and a plurality of level shifters, each of the level shifters being connected between one of the plurality of stages and its associated scanning line for applying a second driving signal to the scanning line in response to the first driving signal, wherein the second driving signal has a larger swing width than the first driving signal, wherein the stages and the level shifters are configured within a single chip.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.